1. Technical Field
The present disclosure relates to the field of integrated circuits and, more specifically, to a system and method for on-chip duty cycle measurement.
2. Description of the Related Art
Continuous developments in the fields of analog and digital circuits (such as microprocessors and high speed communications) need efficient electronic components. Compatibility and the integrity of clock signals within the circuits is one of the important requirements. System clock performance that was previously acceptable is now insufficient to support the high clock speeds of today's circuits.
The duty cycle of high speed clocks is very critical in certain applications such as DDR2 (Double Data Rate 2), where the read/write operation is performed on both rising and falling edges of the clock. Measuring the duty cycle of high speed clocks is thus very critical in these applications. Off chip duty cycle measurement of high speed clocks is not feasible due to speed limitations of IO's and additional distortion caused by intermediate buffers. Hence an on-chip measurement scheme is required to accurately measure the duty cycle of high-speed clock signals.
The measurement of the duty-cycle of a clock signal is an important part of most on-chip PLL BIST solutions. The duty cycle is an important PLL clock specification for DDR2 type applications, and its measurement is a vital part of any PLL BIST solution. Conventional approaches for measuring and correcting duty cycle can be categorized broadly into analog, digital and mixed-signal. Purely analog duty cycle corrector (DCC) circuits like the one proposed by Toru Ogawa, Kenji Taniguchi in ISCAS-2002, Volume 4 titled as “A 50% Duty-Cycle Correction Circuit for PLL Output”, consist of a voltage controlled oscillator (VCO), operational amplifiers (OPAMP), phase detectors and frequency filters that make the design extremely resource-hungry. These circuits are obviously not a good choice when die area is the most important constraint. Moreover, in a typical digital BIST environment, purely analog approaches cannot be used.
The vernier delay line (VDL) has been used extensively for measurement of time and time-to-digital conversion. The technique for measuring Time of Flight (TOF) of particles using the VDL technique is proposed by Antonio H. Chan and Gordon W. Roberts in IEEE Trans. On VLSI Systems, Vol. 12, No. 1, January 2004 titled as “A Jitter Characterization System Using a Component-invariant Vernier Delay Line”. It measures the time between the Start and Stop signals fed to the VDL with a resolution and requires a multi-stage pipelined asynchronous read out circuit. Both these features are unattractive for a BIST implementation due to the area overhead and need for characterization of the test-circuit.
Thus, conventional VDL based time-to-digital converters require an extensive calibration scheme and use two input clocks or start-stop signals. A common short-coming for such systems is that they cannot be used for very high frequencies.
Therefore, there is a need for a system and method for on-chip duty cycle measurement using a single clock signal that neither requires any reference signal for time-period measurement nor requires a calibration phase.